MANIFOLD
Compute ratio for SOTA model training workloads by hardware architecture by EOY 2028
1
Ṁ100Ṁ30
2028
20%
GPU/CPU
20%
FPGA (Reprogrammable ASIC)
59%
Custom ASIC

The ratio of compute (per FLOP) used for the flagship language models of the 10 leading companies/organizations at market close.

Epistemic standards: company/lab announcements, consensus reporting

(Hopefully) forward-compatible definitions:

GPU: a general-purpose CPU specialized to handle embarassingly parallel workload tasks

FPGA: an ASIC that implements logic gates through a reprogrammable medium (currently, LUTs and routing fabric), meaning the logic can be cost-effectively modified after finishing manufacturing, at a price at least one OOM less than manufacturing a new one.

ASIC (excluding FPGAs): a non-reprogrammable IC that directly implements logic that would normally be handled at the programming-language layer in a CPU directly in the digital logic.

Market context
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What if there aren't ten leading companies or orgs by then?

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