Resolution criteria

This market resolves to the first calendar year in which at least 1.0% or more of all computer processors produced globally have a native base general-purpose integer register width (word size) of 128 bits or more (such as RISC-V's RV128 or a future 128-bit x86/ARM equivalent).

Key Definitions and Scope:

• Word Size: Must be the native width of the general-purpose registers (GPRs) used for base integer arithmetic and memory addressing.

• Excluded Technology: The presence of 128-bit or wider SIMD/vector instruction sets (such as SSE, AVX, NEON, or SVE) on an architecture that relies on a 64-bit or 32-bit base does not qualify the processor as 128-bit. Graphics Processing Units (GPUs) and specialized AI accelerators do not qualify unless they function as the primary host CPU running a native 128-bit instruction set.

• Processor Shipments: The denominator includes all shipped microprocessors, including central processing units (CPUs), microcontrollers (MCUs), and mobile application processors (APs).

Verification Sources: Resolution will be determined by data from reputable market research firms (e.g., IDC, Gartner, Mercury Research, Canalys, or WSTS) or official technical documentation from major instruction set architecture (ISA) maintainers and chip design firms (e.g., Intel, AMD, ARM, Apple, RISC-V International).

If a specific chip family transitioning to 128-bit GPRs is verified to have launched, and public shipment numbers for that hardware segment (e.g., a specific tier of server, desktop, or mobile processors) are documented to exceed 1% of the global market in a calendar year, the market will resolve to that year.

Background

The transition from 32-bit to 64-bit computing in the late 1990s and 2000s was heavily driven by the 4 GB RAM addressing barrier. Because a flat 64-bit address space can theoretically address up to 16 exabytes of memory, there has been little commercial pressure to adopt a native 128-bit base architecture for consumer or enterprise hardware.

While modern CPUs routinely use 128-bit, 256-bit, and 512-bit registers for vector and floating-point math (e.g., AVX-512), their primary control logic and integer execution pipelines remain 64-bit. However, the RISC-V foundation has already drafted a base specification for a 128-bit architecture (RV128), anticipating niche or extreme-scale computing architectures (such as warehouse-scale memory pools or specialized hardware security engines) that may eventually require exceptionally wide registers. This market tracks when, or if, these architectures transition from theoretical standards to representing at least 1% of physical hardware production.

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